1. Field of the Invention
The present invention relates to a dry etching method for etching a predetermined portion of an object in the manufacture of, for example, a semiconductor device.
2. Description of the Related Art
The degree of integration in the integrated circuit included in a micro-electronic apparatus is being increased year by year. With increase in the integration degree, the pattern width in the integrated circuit has become smaller and smaller. Also, the pattern depth has become larger and larger. As a thin film processing technique capable of coping with the trend, a dry etching method under a high vacuum is disclosed in, for example, Published Unexamined Japanese Patent Application Nos. 61-256727 and 62-194623.
The dry etching method includes, for example, a plasma etching method, a sputter etching method, an ECR etching method, a magnetron etching method and a ion beam etching method. In the case of employing the dry etching method in the manufacture of a semiconductor element, the etching rate is increased by the use of a halogen-containing gas such as a Freon gas. Thus, the dry etching is employed in a reactive ion etching (RIE) method. The RIE method permits achieving an anisotropic etching while maintaining a high selectivity, i.e., ratio of the etching rate of a material to be etched to that of a photoresist, and also permits a high etching rate, leading to a high productivity.
Various ideas have been proposed in an attempt to improve the etching rate, etching selectivity, etc. in the dry etching method. For example, a method of improving the etching rate of silicon and silicon dioxide while suppressing the etching rate of a photoresist is disclosed in "1990 Symposium of Dry Process Session V-3 p 105-109". According to the method disclosed in this prior art, a fluorine-containing gas such as a CHF.sub.3 gas is used as an etching gas, and the substrate temperature is set lower than 0.degree. C. The particular method is highly effective in the case of etching a silicon film or simultaneously etching a silicon substrate and a silicon dioxide film.
On the other hand, a method of improving the etching rate of silicon while suppressing the etching rate of silicon dioxide and photoresist is disclosed in a monthly magazine "Semiconductor World, 1988, 1, page 58". In this prior art, SF.sub.6 is used as an etching gas, and the substrate temperature is controlled at -100.degree. to -130.degree. C. during the etching treatment. The particular method is effective in the case of etching a silicon film and a silicon substrate alone without etching a silicon dioxide film.
However, any of the prior arts exemplified above gives rise to a serious problem in the case of etching, for example, a silicon dioxide film alone without etching a silicon substrate and photoresist, as follows.
Suppose an etching treatment is employed for forming contact holes in a semiconductor element comprising a silicon substrate, a silicon dioxide layer and a photoresist layer each formed on the substrate, diffusion layers formed within the substrate, and a poly-Si wiring formed within the silicon dioxide layer. In this case, the etching amount should be small in the region for exposing the surface of the poly-Si wiring, and should be large in the region for exposing the surface of the diffusion layer. It follows that, in order to form these contact holes simultaneously in a single etching treatment, it is necessary for the etching rate of poly-Si to be very low and for the etching rate of silicon dioxide to be very high. In other words, the etching selectivity, i.e., a ratio of the silicon dioxide etching rate to the poly-Si etching rate, is required to be very high. However, the etching selectivity of SiO.sub.2 to poly-Si is at most about 13 in the conventional technique. This implies that the poly-Si wiring continues to be etched with an etching rate 1/13 time as high as that of SiO.sub.2 even after formation of a contact hole to expose the poly-Si wiring.
A similar problem takes place also in the case where a SiO.sub.2 film formed on a silicon substrate is overetched to ensure formation of a contact hole. Specifically, the silicon substrate is also etched during the over-etching step with an etching rate 1/13 time as high as the SiO.sub.2 etching rate.
Recently, it is necessary to decrease the depth of a p-n junction layer formed below a contact hole with increase in the integration degree of, for example, an MOLSI element. As a result, a serious problem is taking place that the silicon substrate is etched during the over-etching step to collapse the p-n junction layer.